The present invention relates generally to capacitor banks adapted to provide a variable capacitance to an electronic circuit. More particularly, the present invention relates to a method and apparatus for providing a controllable capacitance value for a high frequency voltage controlled oscillator (VCO).
For a VCO, the resonant frequency of operation is determined by the equation:
                              f          =                      1                          2              ⁢              π              ⁢                              LC                                                    ,                            (        1        )            where L and C are the inductance and capacitance of the resonant circuit, respectively. In some conventional systems operating in the kHz range, the variable capacitance value C is selected using a varactor. In other systems, a capacitor bank with a number of fixed capacitance values is utilized in conjunction with a varactor, which provides the variable capacitance.
In order to provide a series of capacitance values for a VCO, a series of capacitor cells are connected in parallel to form a capacitor bank. FIG. 1 is a simplified schematic diagram illustrating a conventional capacitor cell. As illustrated in FIG. 1, conventional capacitor cell 100 includes two metal-insulator-metal (MIM) capacitors 110 and 112 in series with an NMOS transistor 114 serving as a switch. Transistor 130 and resistor 132 are utilized to establish a biasing condition for node 140 and transistor 134 and resistor 136 are utilized to establish a biasing condition for node 142.
There are two modes of operation for the conventional capacitor cell 100 illustrated in FIG. 1. In the first mode of operation, the NMOS transistor 114 is OFF. In this mode, the single-ended capacitance seen by node 120 includes the parasitic source-to-bulk capacitance (CSB) or the parasitic drain-to-bulk (CDB) (not shown) associated with NMOS transistor 114 plus the parasitic source-to-gate capacitance (CSG) or the parasitic drain-to-gate capacitance (CDG) (not shown) associated with NMOS transistor 114. In the second mode of operation, the NMOS transistor 114 is ON. In this mode, the single-ended capacitance seen by node 120 is approximately equal to the capacitance of MIM capacitor 110. In the second mode, the parasitic capacitances are negligible. The same description equally applies to node 122.
Hence, the overall change in capacitance available using the conventional capacitor cell 100 is approximately equal to the difference between the capacitance of the MIM capacitor 110 and the parasitic capacitances. This difference is approximately equal to the capacitance of the MIM capacitor 110.
In current applications, including applications such as WLAN 802.11a/b/g applications, there is a need to form capacitor banks with minimum capacitance resolution on the order of a few femtoFarads (fF), for example, 2-5 fF. In particular, high frequency operations at, for example, 12 GHz, utilize minimum capacitance values in this range. However, if a capacitor bank is implemented using a conventional capacitor cell as illustrated in FIG. 1, including MIM capacitors characterized by such small capacitance values, variations in the capacitor fabrication process will lead to large random capacitance variations, adversely impacting system performance. Thus, there is a need in the art for improved methods and systems for providing variable capacitance values.